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1435 W University Dr, Boise, ID 83706

https://boisestate.campusgroups.com/rsvp?id=390126
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Join us on Friday, October 17, at 1:30 p.m. to learn about Professor Parsons' research. Light refreshments will be provided.ABSTRACT: The shrinking of semiconductor devices, commonly marked by nanometer nodes, is now moving into the Ångstrom era, where material elements will be only hundreds of atoms wide and a few atoms thick. To augment common lithographic patterning, manufacturers are turning to area-selective deposition, ASD, to directly form device elements using molecular recognition and surface chemical contrast with Ångstrom-scale precision. At the industrial scale, a single ASD process step can create billions of nanometer-sized features aligned with atomic-scale precision across a full 300 mm diameter silicon wafer. Area-selective silicon epitaxy is used routinely for transistor contacts, but extension to other materials is needed. Recently, we found that ASD could be achieved at <300°C by combining chemical etching with atomic layer deposition so that deposition and etching occur simultaneously in parallel. For a range of materials and process conditions, thermodynamic modeling confirms that deposition and etching are both energetically favorable. Akin to high temperature selective epitaxy, the resulting net deposition is inherently self-aligned with the pre-patterned starting surface because the etching reaction locally consumes the deposition reactant, thereby avoiding unwanted nuclei. Using simultaneous deposition and etching, we show area-selective deposition of tungsten on nanopatterned surfaces. Modeling and initial experimental results show that the concept extends to a range of other material systems, indicating that simultaneous deposition and etching provides opportunities for low temperature bottom-up self-aligned patterning for electronic and other nanoscale systems.---Event Details: boisestate.campusgroups.com/rsvp?id=390126

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